1. Comer D J, Comer D T. Using the weak inversion region to optimize input stage design of CMOS op amps. IEEE Transactions on Circuits and Systems -II: Express Briefs, 2004, 51(1): 8-14
2. Vittoz E A. Weak inversion for ultra low-power and very low-voltage circuits. Proceedings of the IEEE Asian Solid-State Circuits Conference (A-SSCC’09), Nov 16-18, 2009, Taipei, China. Piscataway, NJ, USA: IEEE, 2009: 129-132
3. Enz C. An MOS transistor model for RF IC design valid in all regions of operation. IEEE Transactions on Microwave Theory and Techniques, 2002, 50(1): 342-359
4. Toole B, Plett C, Cloutier M. RF circuit implications of moderate inversion enhanced linear region in MOSFETs. IEEE Transactions on Circuits and Systems-I: Regular Papers, 2004, 51(2): 319-328
5. Nguyen T K, Kim C H, Ihm G J, et al. CMOS low-noise amplifier design optimization techniques. IEEE Transactions on Microwave Theory and Techniques, 2004, 52(5): 1433-1442
6. Shameli A, Heydari P. Ultra-low power RFIC design using moderately inverted MOSFETs: an analytical/ experimental study. Proceedings of the IEEE Radio Frequency Integrated Circuits Symposium (RFIC’06), Jun 11-13, 2006, San Francisco, CA, USA. Piscataway, NJ, USA: IEEE, 2006: 4p
7. Kim Y J, Eo Y S, Baek D. A 5.4 mW concurrent low noise CMOS LNA for L1/L5 GPS application. IEICE Electronics Express, 2009, 6(1): 14-19
8. Svelto F, Deantoni S, Montagna G, et al. Implementation of a CMOS LNA plus mixer for GPS applications with no external components. IEEE Transactions on Very Large Scale (VLSI) Systems, 2001, 9(1): 100-104
9. Leroux P, Janssens J, Steyaert M. A 0.8-dB NF ESD- protected 9-mW CMOS LNA operating at 1.23 GHz. IEEE Journal of Solid-State Circuits, 2002, 37(6): 760-765 |